Technical Field
The present disclosure relates to phase-change memories, and more generally memories in which each memory cell comprises a selection transistor and a variable-impedance element which is able to exhibit a number of different states detectable by an impedance measurement. Depending on whether the element is able to preserve its state when its power supply is turned off, the memory is either volatile or nonvolatile.
Description of the Related Art
FIGS. 1A and 1B schematically show in cross section a semiconductor substrate SUB on which has been formed a memory cell MC11 comprising a variable resistance element VZ. FIG. 1A is a longitudinal cross-sectional view of the plane AA′ indicated in FIG. 1B, and FIG. 1B is a transverse cross-sectional view of the plane BB′ indicated in FIG. 1A. The memory cell MC11 comprises a selection transistor comprising a gate GT, (drain or source) conduction regions DDP and SDP on either side of the gate GT, and a channel region under the gate GT between the conduction regions DDP, SDP. The gate GT is produced in a layer made of poly silicon formed on an insulating layer GO deposited on the substrate SUB. The regions DDP, SDP are formed by implanting dopants into the substrate SUB on each side of the gate GT. The memory cell MC11 is covered with a dielectric insulator DI. The conduction region SDP is connected to a source line SL by way of a via passing through the insulating layer D1. The gate GT forms a word line WL lying parallel to the source line SL. The variable-resistance element VZ is formed in the insulating layer D1 and is connected to the conduction region DDP by way of a via formed in the insulating layer D1. The variable-resistance element VZ is connected to a bit line BL formed on the surface of the insulating layer DI by way of a via BC formed in the insulating layer D1. The bit line BL runs perpendicular to the word line WL and source line SL. The memory cell is isolated from adjacent memory cells (or other circuit elements formed on the substrate SUB) by shallow trench isolations STI1 parallel to the gate GT, and shallow trench isolations STI2 perpendicular to the gate GT. The trench isolations STI1 may be replaced by transistor gates (such as the gate GT) that are biased so as to maintain the associated transistor in the off state (not shown).
The variable-resistance element VZ is made of a material able to pass from an amorphous phase to a crystalline phase and vice versa, under the effect of heat. In its amorphous form, the element VZ has a high resistance, and in the crystalline form its resistance is low. The element VZ is therefore associated in series with a heating element HT that heats up under the effect of a current flow. The amorphous form is obtained by applying a current peak to the heating element HT, whereas the crystalline form is obtained by a slower cooling of the element VZ achieved by gradually decreasing the current flowing through the heating element HT. Certain phase-change materials may be controlled to exhibit more than two phases having different resistances, thereby making it possible to store a plurality of bits in a single memory cell.
FIG. 2 shows the electric circuit of one portion of a memory plane comprising memory cells such as the memory cell MC11 shown in FIGS. 1A and 1B. The memory plane comprises word lines WL, source lines SL parallel to the word lines WL and bit lines perpendicular to the word lines WL and to the source lines SL. Each memory cell MC11 comprises a selection transistor ST comprising a (source or drain) conduction terminal connected to one terminal of a variable-resistance element VZ the other terminal of which is connected to one of the bit lines BL. The other conduction terminal of the selection transistor ST is connected to one of the source lines SL, and the gate terminal of the transistor ST is connected to one of the word lines WL.
To decrease the area occupied by each memory cell, it has been proposed to produce the memory cells in pairs sharing one and the same conduction region SDP connected to one source line SL, as in FIG. 2. In this embodiment, the trench isolation ST1 to the left in FIG. 1A is replaced by a gate, such as the gate GT, forming the gate of the selection transistor of the other memory cell of the pair of memory cells.
It would be desirable to further decrease the substrate area occupied by a memory cell comprising a variable-resistance element.